Sub-pages:

When we completed the last draft of our block diagram, we sectioned off related pieces for the sake of testing and layout.  Here’s a brief description of what each section does, as well as a link to the section subcell details.

Section A - Dependency checking unit. This section includes all of the comparators needed to feed the dependency checker PLA with infomation regarding whether two instructions have registers or memory locations in common with each other. The PLA itself is also a part of this section.

Section B - ALU / Jump correction.  This section handles computing the new jump offset in the case a jump is moved in the instruction block. It also contains the “candidate register,” which is the register that stores the instruction that is a candidate for filling a latency hole.

Section C - Candidate instruction selection.  This section has a 5-bit adder to patch up a jump offset if the jump changes position in the instruction block due to some other instruction filling the latency hole.  This is also where you’ll find the reorder register, a temporary storage location for instructions as they are shuffled around in memory.

Section D - Output unit.  This small unit handles multiplexing the output and protecting the bus with an array of T-gates.

Section E - Dependency memory.  This section stores an array of bits marking whether or not a particular instruction has some dependency and is rendered immobile.

Section F - Memory address select.  This section multiplexes between four possible contentions for choosing a memory-access address.

Section G - Algorithm controller (algcont). This is the algorithm controller, and it sits by itself.  Its position near the corner of the chip gives it close access to a number of I/O pads for outputting state bits - a technique we plan on using for testing next semester.

Section H - Head instruction register.  Here you will find a register that contains the “head” instruction, against which other instructions are compared for dependence.