You might have noticed from reading previous sections that we are using Programmable Logic Arrays as well as Finite State Machines. The former is essentially an unclocked version of the latter - but having PLA tools at our disposal has helped us with the boolean equations of the dependency checker, and other combinational logic such as decoders and multiplexers. More information on how we used the PLA tools with the dependency checker is covered under the Instruction Set section on Data Dependencies.

Below are images of our PLAs, and beside each image is a link to the “EQN” file that describes the PLA. If you click on the image thumbnail it will open a larger version of the image.

Our instruction scheduler is a very control-based processor, examining data as well as manipulating it. We had to use several FSMs for the nested-loop structure of our algorithm, which includes the algorithm itself as well as three counters that operate the three nested loops. This page details the hardware implementation of these FSMs, whereas the Algorithm FSM section details the algorithm from a higher level.

Below are images of the Algorithm Controller, the X Counter, the Y counter, and the Trace Counter. Beside each is a link to the “meg” file that describes the FSM.  Click on the image for a larger version.