Irsim Testing

Sub-pages:

To maintain our confidence in the functionality of our design we have been testing during the entire development cycle.  In particular, we have run the large “sections” of our processor through rigorous Irsim, crystal and spice analysis to verify functionality.  Tests of the smallest units are excluded here, as is the test on the dependency checker.  Tests of the entire chip can be found here.  As an aside we were able to use the LabVIEW simulator we wrote to generate test cases for the dependency checker and Section A. Each test result is shown below, with a link to the “CMD” file to the right.  Click on the thumbnail for a larger picture.

Note: To get a better understanding of what each section does, visit Sections under Circuit Layout.

Section A - Dependency checking unit
CMD file

Section B - ALU / Jump correction
CMD file

Section C - Candidate instruction selection
CMD file

Section D - Output unit
CMD file

Section E - Dependency memory
CMD file

Section F - Memory address select
CMD file

Section G - Algorithm controller (algcont)
CMD file

Section H - Head instruction register
CMD file