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We have developed a compact but thorough instruction set that we feel will exercise our instruction scheduler well.  Our current instruction set design is shown below, and is taken from our Milestone 3 Report.

The ARSe instruction set is an 8-bit instruction set with the first two bits as the opcode and the remaining six bits used to encode source and sink registers, immediates, offsets, etc. Note that there are four registers ($r0-$r3) for usage.  The instruction set became extended when we decided to use the last bit of a “memop” instruction to distinguish between loads and stores, and the last bit of a “jump” instruction to distinguish between jumps and jump destinations.

The set is composed of four types of commands:

memop (01) - loads and stores - Loads take the value at a specified memory address and place it into a register, while stores take the value in a register and place it into a specified memory address. These operations have a two-cycle clock latency, thus creating a need to schedule independent instructions in the “latent position” following the memops.  A store is specified by setting the extended opcode bit.

Ex:
lw $r1, 0x7  --> 0 1 0 1 1 1 1 0
sw $r3, 0x4  --> 0 1 1 1 1 0 0 1
 

binop (11) - operations that access up to three registers (example: add $r1, $r2, $r3)

Ex:
add $r1, $r2, $r3 --> 1 1 0 1 1 0 1 1
sub $r3, $r0, $r2 --> 1 1 1 1 0 0 1 0
 

unop (10) - operations that access two registers (example: addi $r1, $r2, 2)

Ex:
addi $r1, $r2, 2 --> 1 0 0 1 1 0 1 0
subi $r2, $r1, 3 --> 1 0 1 0 0 1 1 1
 

jump (00) - A jump instruction skips portions of code and executes instructions beginning at the specified offset.  This instruction is a general form for all jump instructions, potentially including conditional jump instructions, procedure calls, etcetera.  For example, j 0xc jumps ahead 12 words, executes that statement and continues onward.  In this instruction set, the statement to which j jumps must be jd, a jump destination.  The jd instruction is specified by setting the extended opcode bit.

Ex:
00000 j 0xc --> 0 0 0 1 1 0 0 0
00001 add $r1, $r2, $r3 --> 1 1 0 1 1 0 1 1
00010 addi $r1, $r2, 2 --> 1 0 0 1 1 0 1 0
…
01100 jd --> 1 0 0 0 0 0 0 1
01101 sub $r1, $r2, $r3 --> 1 1 0 1 1 0 1 1
01110 subi $r2, $r1, 3 --> 1 0 1 0 0 1 1 1

Register values are not guaranteed after a jump, so the user should store any necessary values to memory before using the jump instruction.
 

However these instructions can’t be reordered without considering data hazards between instructions.  Click here to visit the section detailing data dependencies.