Entire Chip Testing


		We finalized our project with a full test of the chip through the I/O pads, and we have verified the functionality of the entire chip. You can click on the thumbnails on the left to view a particular Irsim simulation. The test CMD file is linked underneath the Irsim thumbnail, and the instruction block used for testing is in text in the middle. The thumbnails on the far right are the Omnilab tests on our fabricated processor. Click on the thumbnail for a larger image of the test, or click on the links for the memory programming and memory reading operations done before and after the actual test (when available). Tests on the fabricated chips matched the results of our simulations (the expected results) in every case.

	This test demonstrates that we can find a latent instruction but no independent instructions, so we should never reorder instructions in memory.




		onelatnoindep.cmd


	binop $r0, $r0, $r0 binop $r0, $r0, $r0 binop $r0, $r0, $r0 load $r1, 0 binop $r2, $r1, $r0 binop $r3, $r2, $r0 binop $r3, $r2, $r0 binop $r3, $r2, $r0

		input


	binop $r0, $r0, $r0 binop $r0, $r0, $r0 binop $r0, $r0, $r0 load $r1 binop $r2, $r1, $r0 binop $r3, $r2, $r0 binop $r3, $r2, $r0 binop $r3, $r2, $r0

		output




		memory before memory after (unchanged)


	This test has one latency and an independent instruction further down the block. Reordering this independent instruction causes the jump to move down one and its offset gets patched.




		reordjup1.cmd


	binop $r0, $r0, $r0 binop $r0, $r0, $r0 load $r1, 7 binop $r0, $r0, $r1 store $r0, 5 j 10 binop $r3, $r3, $r3 binop $r0, $r0, $r0

		input


	binop $r0, $r0, $r0 binop $r0, $r0, $r0 load $r1, 7 binop $r3, $r3, $r3 binop $r0, $r0, $r1 store $r0, 5 j 9 binop $r0, $r0, $r0

		output




		memory before memory after (n/a)


	This test has a latency at the end of the instruction block which can’t be filled. This tests one of the boundary cases of our processor




		latentlast.cmd


	j 0 binop $r3, $r3, $r3 unop $r2, $r2, 2 j 12 binop $r0, $r3, $r0 unop $r2, $r2, 2 unop $r1, $r1, 1 load $r0, 0

		input


	j 0 binop $r3, $r3, $r3 unop $r2, $r2, 2 j 12 binop $r0, $r3, $r0 unop $r2, $r2, 2 unop $r1, $r1, 1 load $r0, 0

		output




		memory before memory after (unchanged)


	In this test the only instruction that can fill the latency is the jump, but the jump is referencing memory as far ahead as is possible - thus it can’t be moved any higher, and no reordering is performed.




		jtestoverflow.cmd


	binop $r2, $r2, $r2 store $r1, 10 binop $r1, $r3, $r3 binop $r1, $r1, $r0 j 15 jd binop $r3, $r3, $r3 binop $r3, $r3, $r3

		input


	binop $r2, $r2, $r2 store $r1, 10 binop $r1, $r3, $r3 binop $r1, $r1, $r0 j 15 jd binop $r3, $r3, $r3 binop $r3, $r3, $r3

		output




		memory before memory after (n/a)


	There are no latencies in this code block, so nothing is reordered




		nolattest.cmd


	binop $r2, $r2, $r2 binop $r1, $r1, $r1 binop $r0, $r0, $r0 binop $r3, $r3, $r3 binop $r3, $r3, $r3 binop $r2, $r2, $r2 j 12 binop $r0, $r3, $r0

		input


	binop $r2, $r2, $r2 binop $r1, $r1, $r1 binop $r0, $r0, $r0 binop $r3, $r3, $r3 binop $r3, $r3, $r3 binop $r2, $r2, $r2 j 12 binop $r0, $r3, $r0

		output




		memory before memory after (unchanged)


	This test has multiple latencies, but only one of them can be filled. The last store here can be filled with the binop following it since they’re not dependent - but since the independent binop is already filling the latency, it just gets moved “in place.”




		latindepfoltest.cmd


	binop $r2, $r2, $r2 store $r1, 2 store $r1, 2 store $r1, 2 binop $r0, $r0, $r0 binop $r0, $r0, $r0 binop $r3, $r3, $r3 binop $r2, $r2, $r2

		input


	binop $r2, $r2, $r2 store $r1, 2 store $r1, 2 store $r1, 2 binop $r0, $r0, $r0 binop $r0, $r0, $r0 binop $r3, $r3, $r3 binop $r2, $r2, $r2

		output




		memory before memory after (n/a)


	There is a single latency in the following block, and an independent binop instruction can be moved from below to fill the latency.




		latdeptest.cmd


	binop $r2, $r2, $r2 store $r1, 10 binop $r1, $r3, $r3 binop $r1, $r1, $r0 binop $r2, $r0, $r0 jd binop $r3, $r3, $r3 binop $r3, $r3, $r3

		input


	binop $r2, $r2, $r2 store $r1, 10 binop $r2, $r0, $r0 binop $r1, $r3, $r3 binop $r1, $r1, $r0 jd binop $r3, $r3, $r3 binop $r3, $r3, $r3

		output




		memory before memory after


	There is a single latency in the following block, and an independent jump instruction can be moved in from below. The jump address gets patched up to reflect its new position.




		jmovetest.cmd


	binop $r2, $r2, $r2 store $r1, 10 binop $r1, $r3, $r3 binop $r1, $r1, $r0 j -16 jd binop $r3, $r3, $r3 binop $r3, $r3, $r3

		input


	binop $r2, $r2, $r2 store $r1, 10 j -14 binop $r1, $r3, $r3 binop $r1, $r1, $r0 jd binop $r3, $r3, $r3 binop $r3, $r3, $r3

		output




		memory before memory after


	We created this final test during the testing process, and it was never simulated with Irsim due to the difficulties of having to simulate external memory accesses. The test has two latencies, both of which can benefit from reording. You can see in the test that memory is written back to two separate times. The first time two instructions are reordered and the second time three are.




		memory before memory after


	binop $r0, $r0, $r0 load $r0, 0 binop $r0, $r2, $r0 unop $r3, $r3, 4 load $r1, 5 unop $r1, $r1, 0 binop $r1, $r1, $r1 binop $r0, $r0, $r0

		input


	binop $r0, $r0, $r0 load $r0, 0 unop $r3, $r3, 4 binop $r0, $r2, $r0 load $r1, 5 binop $r0, $r0, $r0 unop $r1, $r1, 0 binop $r1, $r1, $r1

		output