Script started on Fri Dec 15 08:21:27 2000
Fri Dec 15 08:21:27 CST 2000
lamprey% crystal SECTIONE.sim Crystal, v.2
: build SECTIONE.sim
[0:00.0u 0:00.0s 57k]
: crystal SECTIONE.sim                    source SECTIONE.cryvec
: option graphics magic units 1.0
[0:00.0u 0:00.0s 66k]
: inputs trace0 trace1 trace2 y0 y1 y2 EnableY clkA clkB wd lfbar 
[0:00.0u 0:00.0s 66k]
: outputs dep0 dep1 dep2 dep3 dep4 dep5 dep6 dep7 depout 
[0:00.0u 0:00.0s 66k]
: delay trace0 -1 0
Marking transistor flow...
Setting Vdd to 1...
Setting GND to 0...
(1883 stages examined.)
[0:00.1u 0:00.0s 99k]
: delay trace0 0 -1
More than 5 transistors in series, see dep1 (see source at -103,-565).
More than 5 transistors in series, see dep1 (see source at -103,-565).
More than 5 transistors in series, see dep1 (see source at -103,-565).
More than 5 transistors in series, see dep1 (see source at -103,-565).
More than 5 transistors in series, see dep2 (see source at 9,-565).
More than 5 transistors in series, see dep2 (see source at 9,-565).
More than 5 transistors in series, see dep2 (see source at 9,-565).
More than 5 transistors in series, see dep2 (see source at 9,-565).
More than 5 transistors in series, see dep3 (see source at 121,-565).
More than 5 transistors in series, see dep3 (see source at 121,-565).
No more messages of this kind will be printed.....
(378 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay trace1 -1 0
(35 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay trace1 0 -1
(36 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay trace2 -1 0
(35 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay trace2 0 -1
(42 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay y0 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay y0 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay y1 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay y1 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay y2 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay y2 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay wd -1 0
(2 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay wd 0 -1
(2 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay lfbar -1 0
(3 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay lfbar 0 -1
(11 stages examined.)
[0:00.0u 0:00.0s 99k]
: delay clkA  0 -1
(6450 stages examined.)
[0:00.4u 0:00.0s 117k]
: delay clkB 0 -1
(1318 stages examined.)
[0:00.1u 0:00.0s 118k]
: delay EnableY -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 118k]
: critical
Node depout is driven high at 153.34ns
      ...through fet at (-67, -564) to s2s_0/deptable_0/deptablecell_1/OUT
      ...through fet at (-83, -539) to Vdd after
    s2s_0/deptable_0/deptablecell_1/IN is driven low at 144.40ns
      ...through fet at (-116, -565) to GND after
    s2s_0/deptable_0/deptablecell_1/IN1 is driven high at 143.58ns
      ...through fet at (-152, -561) to indata
      ...through fet at (-264, -561) to s2s_0/deptable_0/deptablecell_0/IN1
      ...through fet at (-245, -561) to dep0
      ...through fet at (-215, -539) to Vdd after
    s2s_0/depinv_0/OUT is driven high at 69.58ns
      ...through fet at (-244, -525) to Vdd after
    w0 is driven low at 69.07ns
      ...through fet at (-217, -503) to s2s_0/deplogic_7/memnand2_0/a_0_n21#
      ...through fet at (-217, -496) to GND after
    s2s_0/deplogic_7/memnand2_0/A is driven high at 67.36ns
      ...through fet at (-176, -525) to Vdd after
    qls0 is driven low at 66.86ns
      ...through fet at (-182, -487) to GND after
    s2s_0/depqualand_0/memorinv_0/A is driven high at 66.37ns
      ...through fet at (-164, -456) to Vdd after
    ls0 is driven low at 65.91ns
      ...through fet at (-253, -348) to GND after
    3x8decoder_0/a_159_n151# is driven high at 64.11ns
      ...through fet at (-253, -280) to Vdd after
    3x8decoder_0/a_22_n61# is driven low at 62.38ns
      ...through fet at (-142, -259) to GND after
    3x8decoder_0/a_44_n80# is driven high at 61.90ns
      ...through fet at (-138, -319) to Vdd after
    3x8decoder_0/a_40_n101# is driven low at 61.30ns
      ...through fet at (-132, -293) to GND after
    m0 is driven high at 60.45ns
      ...through fet at (-51, -251) to muxlatch_0/muxlatinv_0/IN
      ...through fet at (-32, -253) to out0
      ...through fet at (9, -257) to y0 after
    small5inv_0/A is driven high at 49.64ns
      ...through fet at (-21, -185) to vertlatch_0/latchinv_0/IN
      ...through fet at (-40, -185) to delayY
      ...through fet at (65, -185) to vertlatch_1/latchinv_0/IN
      ...through fet at (84, -185) to vertlatch_1/data_in
      ...through fet at (134, -185) to vertlatch_2/latchinv_0/IN
      ...through fet at (153, -185) to EnableY after
    clkB is driven high at 0.00ns
[0:00.0u 0:00.0s 118k]
: critical -g SECTIONE.crymag
[0:00.0u 0:00.0s 118k]
: critical 2
Node depout is driven high at 152.69ns
      ...through fet at (-67, -564) to s2s_0/deptable_0/deptablecell_1/OUT
      ...through fet at (-83, -539) to Vdd after
    s2s_0/deptable_0/deptablecell_1/IN is driven low at 143.74ns
      ...through fet at (-116, -565) to GND after
    s2s_0/deptable_0/deptablecell_1/IN1 is driven high at 142.92ns
      ...through fet at (-142, -540) to indata
      ...through fet at (-264, -561) to s2s_0/deptable_0/deptablecell_0/IN1
      ...through fet at (-245, -561) to dep0
      ...through fet at (-215, -539) to Vdd after
    s2s_0/depinv_0/OUT is driven high at 69.58ns
      ...through fet at (-244, -525) to Vdd after
    w0 is driven low at 69.07ns
      ...through fet at (-217, -503) to s2s_0/deplogic_7/memnand2_0/a_0_n21#
      ...through fet at (-217, -496) to GND after
    s2s_0/deplogic_7/memnand2_0/A is driven high at 67.36ns
      ...through fet at (-176, -525) to Vdd after
    qls0 is driven low at 66.86ns
      ...through fet at (-182, -487) to GND after
    s2s_0/depqualand_0/memorinv_0/A is driven high at 66.37ns
      ...through fet at (-164, -456) to Vdd after
    ls0 is driven low at 65.91ns
      ...through fet at (-253, -348) to GND after
    3x8decoder_0/a_159_n151# is driven high at 64.11ns
      ...through fet at (-253, -280) to Vdd after
    3x8decoder_0/a_22_n61# is driven low at 62.38ns
      ...through fet at (-142, -259) to GND after
    3x8decoder_0/a_44_n80# is driven high at 61.90ns
      ...through fet at (-138, -319) to Vdd after
    3x8decoder_0/a_40_n101# is driven low at 61.30ns
      ...through fet at (-132, -293) to GND after
    m0 is driven high at 60.45ns
      ...through fet at (-51, -251) to muxlatch_0/muxlatinv_0/IN
      ...through fet at (-32, -253) to out0
      ...through fet at (9, -257) to y0 after
    small5inv_0/A is driven high at 49.64ns
      ...through fet at (-21, -185) to vertlatch_0/latchinv_0/IN
      ...through fet at (-40, -185) to delayY
      ...through fet at (65, -185) to vertlatch_1/latchinv_0/IN
      ...through fet at (84, -185) to vertlatch_1/data_in
      ...through fet at (134, -185) to vertlatch_2/latchinv_0/IN
      ...through fet at (153, -185) to EnableY after
    clkB is driven high at 0.00ns
[0:00.0u 0:00.0s 118k]
: critical -g SECTIONE.cry2mag 2
[0:00.0u 0:00.0s 118k]
[0:00.0u 0:00.0s 118k]
: quit
[0:00.6u 0:00.1s 118k] Crystal done.
lamprey% exit
script done on Fri Dec 15 08:21:54 2000