Script started on Fri Dec 15 08:03:12 2000
Fri Dec 15 08:03:13 CST 2000
lamprey% crystal SECTIOND.sim
Crystal, v.2
: build SECTIOND.sim
[0:00.0u 0:00.1s 22k]
: source SECTIOND.cryvec
: option graphics magic units 1.0
[0:00.0u 0:00.0s 31k]
: inputs CLKAqualifier a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 XEQYin WRITE2MEMin
[0:00.0u 0:00.0s 31k]
: outputs out0 out1 out2 out3 out4 out5 out6 out7
[0:00.0u 0:00.0s 31k]
: delay CLKAqualifier -1 0
Marking transistor flow...
Setting Vdd to 1...
Setting GND to 0...
(58 stages examined.)
[0:00.0u 0:00.0s 35k]
: delay CLKAqualifier 0 -1
(62 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a0 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a0 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a1 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a1 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a2 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a2 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a3 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a3 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a4 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a4 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a5 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a5 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a6 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a6 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a7 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay a7 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b0 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b0 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b1 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b1 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b2 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b2 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b3 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b3 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b4 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b4 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b5 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b5 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b6 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b6 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b7 -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay b7 0 -1
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay XEQYin -1 0
(1 stages examined.)
[0:00.0u 0:00.0s 38k]
: delay XEQYin 0 -1
(37 stages examined.)
[0:00.0u 0:00.0s 39k]
: delay WRITE2MEMin -1 0
(4 stages examined.)
[0:00.0u 0:00.0s 39k]
: delay WRITE2MEMin 0 -1
(4 stages examined.)
[0:00.0u 0:00.0s 39k]
: critical
Node out0 is driven low at 10.90ns
      ...through fet at (61, 356) to 8bitmux_0/out0
      ...through fet at (19, 355) to a0 after
    smallinv_0/OUT is driven low at 9.88ns
      ...through fet at (33, 414) to GND after
    latchedXEQY is driven high at 7.05ns
      ...through fet at (25, 378) to Vdd after
    buffer_0/a_n17_n19# is driven low at 5.22ns
      ...through fet at (5, 404) to GND after
    buffer_0/IN is driven high at 4.80ns
      ...through fet at (-41, 399) to SECTIONDvertlatch_0/latchinv_0/IN
      ...through fet at (-60, 399) to XEQYin after
    XEQYin is driven high at 0.00ns
[0:00.0u 0:00.0s 39k]
[0:00.0u 0:00.0s 39k]
: quit
[0:00.0u 0:00.1s 39k] Crystal done.
lamprey% exit
script done on Fri Dec 15 08:03:44 2000