The longest delay through our slowest combinational logic is still smaller than the large delay of off-chip memory.  Our processor uses the standard Karplus model of a non-overlapping double clock. We are treating the memory as a big ball of combinational logic, so we expect a memory request that goes out on VaSb to return on a somewhat skewed VaSb.

Additionally, the longest memory access occurs when writing, which we do with a Qb signal.  This signal must be at least 55ns long, so with a four-phase clock this becomes 55 * 4 = 220ns.  This translates to a maximum clock speed of 4.5 Mhz.