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This section details the high-level logic and system timing diagrams as well as Irsim testing of our entire chip and subcells.
- For the block diagram, which details the logic of our Scheduler, go here.
- For the system timing diagram, which follows the Karplus timing model, go here.
- For Irsim testing, visit the eponymous link.
- For testing of our fabricated chip check here.
- And as an additional goodie, we’ve included a LabVIEW-based simulator that you can try yourself. A small “Player” for LabVIEW can be
installed to run the simulator, and all those details are covered here.
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