The best way to understand our cell hierarchy is to navigate through each section’s page where selected subcells are included. For convenience though we will present the hierarchy here, with links to the sections’ page that discusses their subcells.  We have also written out our hierarchy file-by-file here.

Section A contains:

• The dependency checker
• The “comparray” subcell, which contains:
• 2 bit comparators
• 3 bit comparator
• Inverters and eXclusive OR gates common to both

Section B contains:

• “Memory” cells, including:
• meminv, an inverter
• memnor, a nor gate
• memnand, a nand gate
• A qualifying and gate
• A three bit and 5 bit adder, which share the following:
• a two-bit adder
• a one-bit adder
• an adder-specific xor, inverter, nand gates
• a “reversed” version of the previous gates.
• The candidate register, which contains:
• aforementioned memory subcells
• two seperate but similar memory cells, named “88cand” and “candregdos”
• A 5-bit comparator that compares a number to binary “10000”

Section C contains:

• A 5-bit adder with the same subcells as mentioned above
• An 8-bit register, which contains
• A memory cell named “88mem”
• A qualifying and gate

Section D contains:

• An 8-bit Mux, which contains a 2-input Mux
• An 8-bit T-gate, which contains a “tgate”
• A buffer for the Mux control signals
• Inverters of varying size and driving power

Section E contains:

• A 3x8 decoder, generated as a PLA.
• “s2s”, the dependency memory, which uses
• the dependency-customized version of aforementioned memory logic
• a dependency-customized qualifying and gate
• A 3-bit Mux, which contains a 2-input Mux
• Buffers and inverters of various driving power

Section F contains:

• The counters, X counter, Y counter, and Trace counter
• A 3-bit register, which uses 883bitmem
• A 3-bit comparator, with appropriate subcells
• A 3-bit address multiplexor, generated by PLA

Section G contains:

• Itself.  It’s the Algorithm Controller, a PLA and a section all of its own.

Section H contains:

• An 8-bit register, with appropriate subcells
• A 3-input nor gate
• A cell called “latent” that contains
• an inverter
• a specialized nor gate