vector xbits X{0:2} vector ybits Y{0:2} vector tracebits TRACE{0:2} vector yregbits YREG{0:2} vector muxbits MUX{0:1} vector outbits OUT{0:2} ana clkb clka RESTARTX RESTARTY RESTARTTRACE ENABLEX ENABLEY ENABLETRACE SETY SETTRACE ana REVERSEY WRITEYREG muxbits ana xbits LASTX ybits LASTY tracebits LASTTRACE yregbits outbits clock clkb 0 1 0 0 clock clka 0 0 0 1 stepsize 20 | reset counters V RESTARTX 1 0 0 V RESTARTY 1 0 0 V RESTARTTRACE 1 0 0 V ENABLEX 0 0 0 V ENABLEY 0 0 0 V ENABLETRACE 0 0 0 V SETY 0 0 0 V SETTRACE 0 0 0 V REVERSEY 0 0 0 V WRITEYREG 0 0 0 V muxbits 00 00 00 R | sety, settrace, enabletrace until trace=000 V RESTARTX 0 0 0 0 0 0 0 0 0 0 V RESTARTY 0 0 0 0 0 0 0 0 0 0 V RESTARTTRACE 0 0 0 0 0 0 0 0 0 0 V ENABLEX 0 0 0 0 0 0 0 0 0 0 V ENABLEY 0 0 0 0 0 0 0 0 0 0 V ENABLETRACE 0 0 1 1 1 1 1 1 1 1 V SETY 1 0 0 0 0 0 0 0 0 0 V SETTRACE 0 1 0 0 0 0 0 0 0 0 V REVERSEY 0 0 0 0 0 0 0 0 0 0 V WRITEYREG 0 0 0 0 0 0 0 0 0 0 V muxbits 00 01 10 10 10 10 10 10 10 10 R | enabley and storey, wait for indep, check candid type, reorder, since x=y, search again V RESTARTX 0 0 0 0 0 0 V RESTARTY 0 0 0 0 0 0 V RESTARTTRACE 0 0 0 0 0 0 V ENABLEX 0 0 0 0 1 0 V ENABLEY 1 0 0 0 0 0 V ENABLETRACE 0 0 0 0 0 0 V SETY 0 0 0 0 0 0 V SETTRACE 0 0 0 0 0 0 V REVERSEY 0 0 0 1 0 0 V WRITEYREG 1 0 0 0 0 0 V muxbits 01 01 01 01 11 00 R | now back at searching for latent, so go for a few instructions V RESTARTX 0 0 0 0 V RESTARTY 0 0 0 0 V RESTARTTRACE 0 0 0 0 V ENABLEX 1 1 1 1 V ENABLEY 0 0 0 0 V ENABLETRACE 0 0 0 0 V SETY 0 0 0 0 V SETTRACE 0 0 0 0 V REVERSEY 0 0 0 1 V WRITEYREG 0 0 0 0 V muxbits 00 00 00 00 R | say latent found here, so set y and trace, enable trace, wait one state V RESTARTX 0 0 0 0 V RESTARTY 0 0 0 0 V RESTARTTRACE 0 0 0 0 V ENABLEX 0 0 0 0 V ENABLEY 0 0 0 0 V ENABLETRACE 0 0 1 0 V SETY 1 0 0 0 V SETTRACE 0 1 0 0 V REVERSEY 0 0 0 0 V WRITEYREG 0 0 0 0 V muxbits 00 01 10 00 R | and look for dependency until trace=000 V RESTARTX 0 0 V RESTARTY 0 0 V RESTARTTRACE 0 0 V ENABLEX 0 0 V ENABLEY 0 0 V ENABLETRACE 1 1 V SETY 0 0 V SETTRACE 0 0 V REVERSEY 0 0 V WRITEYREG 0 0 V muxbits 10 10 R | enabley and storey, wait, check candid dep, search for y again, so settrace, enabletrace V RESTARTX 0 0 0 0 0 0 0 V RESTARTY 0 0 0 0 0 0 0 V RESTARTTRACE 0 0 0 0 0 0 0 V ENABLEX 0 0 0 0 0 0 0 V ENABLEY 1 0 0 0 0 0 0 V ENABLETRACE 0 0 0 0 0 1 0 V SETY 0 0 0 0 0 0 0 V SETTRACE 0 0 0 0 1 0 0 V REVERSEY 0 0 0 0 0 0 0 V WRITEYREG 1 0 0 0 0 0 0 V muxbits 01 01 01 01 01 10 10 R | and look for dependency until trace=000 V RESTARTX 0 V RESTARTY 0 V RESTARTTRACE 0 V ENABLEX 0 V ENABLEY 0 V ENABLETRACE 1 V SETY 0 V SETTRACE 0 V REVERSEY 0 V WRITEYREG 0 V muxbits 10 R | enabley and storey, wait, check candid dep, check candid type V RESTARTX 0 0 0 0 V RESTARTY 0 0 0 0 V RESTARTTRACE 0 0 0 0 V ENABLEX 0 0 0 0 V ENABLEY 1 0 0 0 V ENABLETRACE 0 0 0 0 V SETY 0 0 0 0 V SETTRACE 0 0 0 0 V REVERSEY 0 0 0 1 V WRITEYREG 1 0 0 0 V muxbits 01 01 01 01 R | go through the re-write cycle until x=y (4 ticks is one cycle) V RESTARTX 0 0 0 0 0 0 0 0 V RESTARTY 0 0 0 0 0 0 0 0 V RESTARTTRACE 0 0 0 0 0 0 0 0 V ENABLEX 0 0 0 0 0 0 0 0 V ENABLEY 0 0 0 0 0 0 0 0 V ENABLETRACE 0 0 0 0 0 0 0 0 V SETY 0 0 0 0 0 0 0 0 V SETTRACE 0 0 0 0 0 0 0 0 V REVERSEY 0 0 0 1 0 0 0 1 V WRITEYREG 0 0 1 0 0 0 1 0 V muxbits 11 11 01 01 11 11 01 01 R | go back to searching for latent and cycle until XLAST, one final wait cycle V RESTARTX 0 0 0 0 V RESTARTY 0 0 0 0 V RESTARTTRACE 0 0 0 0 V ENABLEX 1 0 1 0 V ENABLEY 0 0 0 0 V ENABLETRACE 0 0 0 0 V SETY 0 0 0 0 V SETTRACE 0 0 0 0 V REVERSEY 0 0 0 0 V WRITEYREG 0 0 0 0 V muxbits 11 00 00 00 R